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| UL (R) LSI/CSI LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 LSI RDD 104 (631) 271-0400 FAX (631) 271-0405 January 2000 A3800 SELECTABLE 4 DECADE CMOS DIVIDER FEATURES: * Selectable Divide by 10 or 100 or 1,000 or 10,000 * Clock Input Shaping Network Accepts Fast or Slow Edge Inputs * Active Oscillator Network for External Crystal * Square Wave Output * Output TTL Compatible at +4.5 Volt Operation * High Noise Immunity * Reset * All Inputs Protected * +4.5V to +15V Operation (VDD-VSS) * Low Power Dissipaton * RDD104 (DIP); RDD104-S (SOIC) - See Figure 1 PIN ASSIGNMENT - TOP VIEW DIVIDER SELECT-1 DIVIDER SELECT-2 1 8 VDD (+V) 2 RDD 104 7 OUTPUT VSS (-V) 3 6 CLOCK OUTPUT RESET 4 5 CLOCK INPUT DESCRIPTION OF OPERATION: The RDD104 is a monolithic CMOS four decade divider circuit that advances on each negative transition of the input clock pulse. When the reset input is high the circuit is cleared to zero. The clock input is applied to a three stage inverting amplifier network whose output is brought out so that an external crystal network can be used to form an oscillator circuit. If the clock output is not used,the amplifier acts as an input buffer. Two select inputs are provided which enables the circuit to divide by 10, 100, 1,000 or 10,000. FIGURE 1 MAXIMUM RATINGS: PARAMETER SYMBOL VALUE UNIT Storage Temperature Operating Temperature DC Supply Voltage Voltage at any input TSTG -65 to +150 TA -40 to +85 (VDD - VSS) +18 VIN VSS - 0.5 to VDD + 0.5 C C V V DC ELECTRICAL CHARACTERISTICS: (All voltages referenced to Vss) VDD -40C +25C Quiescent Device Current 4.5V 10V 4.5V 10V 4.5V 10V 4.5V 10V 10 20 0.01 0.01 4.49 9.99 1.3 3.0 10 20 0.01 0.01 4.49 9.99 1.3 3.0 +85C 300 600 0.05 0.05 4.45 9.95 1.3 3.0 UNIT uA Max uA Max V Min V Min V Max V Max V Min V Min The Output Division is selected according to the following truth table: DIVIDER SELECT INPUTS: SELECT 2 SELECT 1 0 0 0 1 1 0 1 1 OUTPUT DIVISION 10,000 1,000 100 10 Output Voltage, Low Level High Level Input Noise Immunity (Low and High) Output Drive Current: N-Channel Sink Current (VOUT = Vss + 0.4V) P-Channel Source Current (VOUT = VDD - 1V) Input Capacitance (any input) 4.5V 10V 4.5V 10V 2.3 5.0 1.1 2.5 1.9 4.0 0.95 2.1 5.0 1.6 3.5 0.8 1.8 mA Min mA Min mA Min mA Min pF Max The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. RDD104-092491 DYNAMIC ELECTRICAL CHARACTERISTICS: (CL = 50pF, Input Rise and Fall Times = 20ns except for Clock, unless otherwise specified.) VDD MIN MAX Clock Input Frequency 4.5V 0 1.5 10V 0 4.0 15V 0 6.0 Clock Input Rise & Fall Times Clock Input Rise & Fall Time, CL = 15pF Clock Output Propagation Delay, CL = 15pF Output Rise & Fall Times 4.5 to 15V 4.5V 10V 4.5V 10V 4.5V 10V 4.5V 10V 4.5V 10V 4.5V 10V 4.5V 10V 4.5V 10V 800 400 No Limit 140 70 300 150 400 200 1500 750 500 250 1400 700 800 400 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20pF 39pF 40pF 10M 100pF PIN 5 UNIT MHz MHz MHz 10M PIN 6 FIGURE 2. MINIMUM PARTS OSCILLATOR CIRCUIT PIN 5 20M Propagation Delay to Output PIN 6 Reset Pulse Width FIGURE 3. TYPICAL OSCILLATOR CIRCUIT WITH TRIM -1 MHZ AND BELOW PIN 5 50pF 10M Reset Removal Time Reset Propagation Delay to Output Select Input Setup Time 56pF PIN 6 FIGURE 4. TYPICAL OSCILLATOR CIRCUIT WITH TRIM - ABOVE 1 MHZ V DD CLOCK INPUT SIGNAL R1 5 V DD FIGURE 5. TYPICAL INPUT If input signals are less than VSS or greater than VDD, a series input resistor, R1, should be used to limit the maximum input current to 2 milliamperes. V SS 3 STAGE INVERTING AMPLIFIER +V CLOCK IN OSCILLATOR EXTERNAL COMPONENTS 5 8 V DD FIGURE 6. RDD 104 BLOCK DIAGRAM -V 3 V SS R CLOCK GENERATOR / 10 / 10 / 10 / 10 CLOCK OUT 6 RESET DIVIDER SELECT-1 4 1 DECODER 1 OUT OF 4 SELECTOR BUFFER 7 OUTPUT DIVIDER SELECT-2 2 RDD104-011000-2 |
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